1. Field of the Invention
The present invention generally relates to methods for manufacturing semiconductor devices. More particularly, this invention relates to methods for manufacturing CMOS devices having a gate stack comprising a metal gate electrode and the CMOS devices made thereof.
2. Description of the Related Technology
Up to now, semiconductor industry remains driven by scaling geometric dimensions of metal-oxide-semiconductor field-effect-transistors (MOSFETs). With traditional MOSFET-technology, using silicon dioxide (SiO2) as gate dielectric and polycrystalline silicon (poly-Si) as gate material, a lot of problems occur when scaling down to 100 nm or below.
As the gate dielectric thickness is reduced, an exponential increase of gate direct tunneling currents occurs. One solution to solve this problem for a 45 nm technology node and beyond is the introduction of so-called high-k dielectrics as gate dielectric. A high-k dielectric is a dielectric featuring a dielectric constant (k) higher than the dielectric constant of SiO2, i.e. k>3.9. High-k dielectrics allow for a larger physical thickness (compared to SiO2) for obtaining a same effective capacitance than can be obtained with a much thinner SiO2 layer. The larger physical thickness of the high-k material will reduce gate leakage currents.
However, for SiO2 oxide thicknesses below 2 nm, a polysilicon (poly-Si) depletion effect starts to become dominant in the poly-Si gate. A solution to this problem is the introduction of metals as gate material. Advantages of metal gates are elimination of the polysilicon depletion effect, very low resistance, no dopant penetration possible and better compatibility with high-k gate dielectrics.
By introducing metal gates, the threshold voltage of the MOSFET becomes controlled by the metal workfunction. Regarding metal gate electrodes, tuning of the workfunction is not straightforward as a different workfunction is needed for NMOS than for PMOS. This requires now a (n-type) metal (replacing poly-Si) that works for nMOSFET (i.e. a workfunction preferably about 4.1 eV (+/− about 0.3 eV)) and a (p-type) metal that works for pMOSFET (i.e. a workfunction preferably about 5.2 eV (+/− about 0.3 eV)). Whereas the workfunction of a polysilicon gate electrode can be tuned by ion implantation, the workfunction of a metal gate electrode is a material property which cannot be changed easily.
The introduction of new gate materials, such as high-k gate dielectrics combined with metal gate electrodes, is not easy, since problems may occur in the traditional gate-first fabrication process like etch and strip. Also high thermal budgets in the gate-first integration scheme can form a problem, such as a shift in the threshold voltage and decreased device reliability. To overcome these high-thermal budgets, a low-temperature process has been introduced, commonly known as the gate-last approach or replacement-gate (RPG) approach. In the gate-last approach the metal gate deposition occurs after the source/drain activation anneals, such that the metal material is not exposed to high temperatures.
Hence, for the integration of high-k gate dielectrics and metal gate electrodes in a complementary metal-oxide-semiconductor (CMOS) device, new alternatives have to be introduced in the process flow. Although already some possibilities are available in the state-of-the-art for the integration of metal gate and high-k dielectric in CMOS devices, there is a need for simplified integration schemes for high-k/metal semiconductor device and more specific for simplified single metal, single dielectric (SMSD) integration schemes and metal/high-k RPG integration schemes.